In a typical computer system of FIG. 1, a core logic circuit 13 such as a chipset, is widely used to control data flows among a central processing unit (CPU) 11, a system memory 12, and a plurality of I/O devices including a 3D graphics accelerator 14 and other I/O devices 15. For example, the CPU 11 accesses data of a system memory 12 or outputs graphing commands to the 3D graphics accelerator 14 via the core logic circuit 13. The system memory, for example, is a dynamic random access memory (DRAM). The core logic circuit 13 includes several interface controllers such as a host controller 130, a DRAM controller 131, an AGP/PCI controller 132 and other I/O interface controllers 133, as can be seen in FIG. 2, The interface controllers 130, 131, 132 and 133 are employed for controlling data exchange between the core logic circuit 13 and respectively the CPU 11, the system memory 12, the 3D graphics accelerator 14 and other I/O devices 15. In general, data flows through different buses to be used. For example, the CPU 11 accesses memory data through a host bus and a memory bus (not shown). Since the newly developed buses, e.g. a USB or an IEEE 1394 interface, are specified for different applications, the pad number of the core logic circuit 13 is large for complying with the requirements. Therefore, a large area of the core logic circuit is required for accommodating the large number of pads. Under this circumstance, although the control circuits of the buses require extremely small area for current semiconductor manufacturing technology, the area of the core logic circuit could not be reduced correspondingly. Such occurrence is called a “pad-limited” phenomenon.
On the other hand, with the increasing demand of 3D graphics, a part of the 3D graphics accelerating task is transferred from the CPU to the 3D graphics accelerator. Therefore, the 3D graphics accelerator 14 becomes larger than ever. Referring to FIG. 3(a), the 3D graphics accelerator 14 generally includes a geometry engine 141 and a rendering engine 142. The geometry engine 141 and the rendering engine 142 are used for doing the transform/lighting and setup/rendering operations, respectively. The geometry engine 141 and the rendering engine 142 are incorporated in a single chip for improving 3D graphics performance. In addition, nowadays, multiple pipelines are widely used in the rendering operation to improve the rending throughput. Therefore, much more logical gates are required to be installed in the 3D graphics accelerator 14, which increases the cost of the 3D graphics accelerator 14. FIG. 3(b) illustrates another design of the 3D graphics accelerator 14. Since the processing speeds of the geometry engine 141 and the rendering engine 142 are different in some cases, a local DRAM 16 for supporting the rendering operation as shown in FIG. 3(a), is provided for buffering the output of the geometry engine 141 so as to prevent such engines from being idle. As known, a sufficient memory bandwidth is required for the operation of the rendering engine 142. The share of the local DRAM as described above might impair the performance of the rendering engine 142 due to the reduction of the memory bandwidth provided for the rendering operation.